1. Field of the Invention
The present invention relates to a method of forming a silicon-on-insulator structure.
2. Description of the Prior Art
The rapid development of many semiconductor devices requires the use of a thin layer of silicon upon an insulating layer, such as silicon dioxide. For the present device technology a silicon-on-insulator (SOI) substrate would have several advantages over bulk silicon substrates. For example devices made on these substrates will be radiation-hard and will show no latch-up effect. There has been a substantial effort made to produce such SOI substrates by a variety of methods including silicon on sapphire, recrystallization of a thin poly silicon layer and implantation of a buried silicon oxide layer. Wafer bonding and subsequent mechanical or chemical thinning is a promising technique to obtain SOI substrates. Since first reports of this technique, for example by J. B. Lasky, "Wafer bonding for silicon-on-insulator technologies", Applied Physics Letters, Volume 48, (1986) pages 78-80 there has been intensive effort to improve this procedure. An overview on recent methods to fabricate a SOI substrate by bonding and thinning is given by J. Haisma, G. A. C. M. Spierungs, U. K. P. Biermann and J. A. Pals in "Silicon-on-Insulator Bonding-Wafer Thinning Technological Evaluations", Japanese Journal of Applied Physics, Volume 28, No. 8, (1989) pages 1426-1443. Many difficulties have been found in the development of a satisfactory bonding process. However, the problems of bubble-free and homogeneous bonding at room temperature have now been virtually solved. For example U.S. Pat. No. 4,883,215 filed Dec. 19, 1988, by U. M. Goesele and R. J. Stengl discloses and claims a method of bubble-free wafer bonding in a non-cleanroom environment using a micro-cleanroom set-up. However, the thinning procedure, necessary to produce the thin semiconductor layer, still suffers from several drawbacks when such process is attempted by prior-art techniques.
A specific method for obtaining a SOI substrate using a bonding and thinning technique is described in U.S. Pat. No. 4,601,779, filed June 24, 1985, entitled "Method of producing a thin silicon-on-insulator layer", by J. R. Abernathey, J. B. Lasky, L. A. Nesbit, T. O. Sedwick, and S. Stiffler. As described in this patent an epitaxial layer is formed on a silicon wafer before any implantation process is carried out. Said wafer is highly doped whereas the epitaxial layer has a low doping density. Then the wafer is implanted in order to create a thin buried etch-stop layer in the epitaxial silicon. After oxidizing this wafer it is bonded to a supporting silicon wafer. By grinding and using an acidic etch the substrate and part of the epitaxial silicon is removed. A second alkaline etching procedure is necessary to remove part of the epitaxial layer and stop on the implanted etch stop. The etch stop layer is removed by yet a third etching step. The remaining part of the epitaxial layer forms the thin silicon layer.
A drawback of the process described by U.S. Pat. No. 4,601,779 is the use of a epitaxial silicon layer. Forming a epitaxial silicon layer is not only expensive and time consuming, it may also create crystal defects (dislocations) in the epitaxial silicon if it is grown on a highly doped substrate. In addition several etching steps are necessary to obtain the SOI-substrate. No prior-art teaches the production of SOI-substrates by wafer bonding without using an epitaxial layer. Furthermore all techniques use a multiplicity of etches and etch stops to produce the SOI-structure.